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XC7A35T-2FTG256I Overview
XC7A35T-2FTG256I is a field-programmable gate array (FPGA) from Xilinx, designed for digital circuitry. It belongs to the Artix-7 family and features 33,280 logic cells, 210 input/output pins, and 1 Mb of internal memory. The FPGA requires a core voltage of 0.95V to 1.05V and an auxiliary voltage of 1.8V to 3.3V, and can operate in temperatures ranging from -40°C to +100°C, making it suitable for use in a variety of applications such as automotive, communications, and industrial automation. The package type for this FPGA is a 256-ball fine-pitch thin grid array (FTG), as indicated by "FTG" in the part number. Overall, XC7A35T-2FTG256I is a versatile FPGA that can handle moderate logic resources and I/O capabilities, making it ideal for a wide range of applications that require high performance and low power consumption.
XC7A35T-2FTG256I Features
Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.
Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.
XC7A35T-2FTG256I Applications
Voice recognition
Embedded Vision
Audio
Enterprise networking
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XC7K160T-2FBG484I Overview
XC7K160T-2FBG484I is a high-performance field-programmable gate array (FPGA) manufactured by Xilinx Inc. It is a member of the Kintex-7 family and features 160,000 logic cells, 16.8 Mb of internal memory, and 500 input/output pins. The FPGA has a core voltage range of 0.95V to 1.05V and an auxiliary voltage range of 1.8V to 3.3V. It can operate in temperatures ranging from -40°C to 100°C, making it suitable for use in a variety of applications such as aerospace, defense, and high-performance computing. The package type for this FPGA is a 484-ball fine-pitch ball grid array (FBGA), as indicated by "FBG" in the part number. Overall, XC7K160T-2FBG484I is a versatile FPGA that can handle complex logic resources and I/O capabilities, making it well-suited for a wide range of high-performance applications.
XC7K160T-2FBG484I Features
Endpoint and Root Port designs
Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offer easy migration between family members in the same package. All packages available in Pb-free and selected packages in the Pb option.
XC7K160T-2FBG484I Applications
Audio
Enterprise networking
Software-defined radios
Solar Energy
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XC7A35T-1FTG256I Overview
33208 logic cells/elements comprise a basic building block. Power for FPGA chips comes from a 1V supply. The development board can be connected to this FPGA module via Surface Mount connections. The device needs a supply voltage between 0.95 and 1.05 volts to function. When the device is in use, FPGA chips are required to maintain the operating temperature within the range of -40°C and 100°C TJ. In this device, there are 170 outputs altogether. This FPGA model is included in Tray as opposed to other FPGA models in order to conserve space. There are 256 terminations altogether. This device offers 1843200 RAM bits, which is the maximum amount available.
XC7A35T-1FTG256I Features
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offer easy migration between family members in the same package. All packages are available in Pb-free and selected packages in the Pb option.
Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.
XC7A35T-1FTG256I Applications
Automotive Applications
Military Temperature
Medical ultrasounds
Software-defined radio
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HC1S60F1020AA FPGAs Overview
HardCopy Stratix structured ASICs, Atera 's second-generatlon HardCopy structured ASICs, are low-cost, high-performance davices with the samearchitecture as the high-density Stratx FPGAs.The combinatlon of Stratk FPAs for prototyping and deslgn verficaton,HardCopy Stratix devicesor high-volume productlon, and the Quartus design sotware beghning w/th verslon 3.0, provide a complete and powerful atemative to ASICdeslgn and development
HardCopy Stratix HC1S60F1020AA devices are architecturaly equivalen! and have the same features as the coresponding Stratix FPGA. Theyofler pin-o-pin compatiblty using the same package as the corresponding Stratx FPCA protlype.Designers can prototype ther design to vertffunctionality with Stralx FPCAs belore seamlessly migrating the proven design to a HardCopy Stratix structured ASIC.
The Quartus l software provides a complete set of nexpenstve and easy-0-use tools for desgning HardCopy Stratx devices. Using the successfuland proven methodology from HardCopy APEX devices, Stratkx HC160F1020AA FPGA designs can be seamlessly and quckly migrated to a lo-cost ASIC alieative. Designers can use the Quartus ll sotvire to design HardCopy Stratix devices to obtain an average of 50% higherperformance and up o 40% owr power consumplion han can be achieved in the coresponding Stratix FPGAs, The migraion process is fulyautomated, roquros minimal customor invovement, and akes approxmalely cight weeks to delver fuly testod HardCopy Stratix prololypes.
Features
HardCopy Stratix devices are manufactured on the same 1.5-V, 0.13 um al-ayer-copper matal fabricathon process up to eight layers of metal) asthe Stratix FPGAS.
Preserves the functlonallty of a configured Stratix device
Pin-compatble wih the Stratix counterparts
On average, 50% faster than their Stratix equivalents
On average, 40% less power consumption than their Stratix equivalents
25 660 t0 79.040 LES
Up to 5.658 408 RAM bits available TiMatrix memory architecture consisting of three RAM block sizes to implement true dual-port memory and first-in-first-out (FIFO) bufers Embedded high speed DSP blocks provide dedicaled implementation of muipliers, mulliply accumulate functions, and finite impulse response(FIR) filters
" Up to 12 PLLs (four enhanced PLLs and eight fast PlLs) per device which provide idnfical features as the FPGA counterparts, induding spreadspecrum, programmabla bandxidth, clock switchover, rea-ime PLL reconfiguration, advanced muliplication, and phase shifing
Supports numerous singleended and diferential liO standards
Supports high-speed networking and comrmunications bus slandards including Rapidl0UTOPIA IV, CSIX,HyperTfransport technology,10GElhemnet XSB1, SPJ4 Phase 2 (POSPHY Lel 4), and SFI4
Differential on-chip termination support for LVOS
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