FPGA vs. CPLD: Main differences between them

Evolution of programming devices

What are Programmable Read Only Memories (PROMs)?

PROMs, also known as programmable read-only memories, are simply memories that can be easily programmed by the user to store a specific pattern. This pattern can represent a state machine, a rudimentary algorithm, or a microprocessor program. Certain PROMs have a one-time programming limit. Other PROMs can be programmed and wiped several times, including EPROMs and EEPROMs. Any combinatorial logic can be implemented using PROMs with a constrained number of inputs and outputs. Flip-flops or microprocessors—or other externally clocked components—must be added in order to implement sequential logic. PROMs also have a tendency to be incredibly slow, making them useless for applications where speed is a concern.  

What are Programmable Logic Arrays (PLAs)?

The speed and input restrictions of PROMs were overcome by Programmable Logic Arrays (PLAs). In a PLA, many inputs are connected to an AND plane, where, depending on how the part is coded, various signal combinations can be logically ANDed together. The OR plane receives the outputs from the AND plane, which are then ORed together in various combinations to generate the desired outputs. Inverters are frequently present at the inputs and outputs to enable the generation of logical NOTs. Although they cannot implement all conceivable combinations like a PROM, these devices can implement many combinatorial functions. They are usually faster and feature a lot more inputs, though.  

What is programmable Array Logic (PALs)?

The PLA has a variant called the Programmable Array Logic (PAL). It has a large, programmable AND plane for ANDing inputs together, just as the PLA. The number of terms that can be ORed together is however constrained by the fixed nature of the OR plane. Latching devices, exclusive ORs, multiplexers, and other fundamental logic components are added to the inputs and outputs. The inclusion of timed components—typically flip-flops—is crucial. Now, a wide range of logic operations, including clocked sequential logic without the requirement for state machines, may be implemented by these devices. This was a significant advancement that made it possible for PALs to largely take the role of ordinary logic in many designs. PALs are also very quick.  

What is CPLD?

The things that complex programmable logic devices (CPLDs) promise to be are exactly what they are. In essence, they are made to resemble a large number of PALs integrated onto a single chip and connected to one another through a crosspoint switch. They are based on the same technology, employ the same programmers and development tools, and can manage a greater volume and complexity of reasoning. The CPLD (complex programmable logic device), which is intermediate in complexity to the SPLD (simple programmable logic device) and FPGA, inherits capabilities from both devices. While less complex than FPGAs, CPLDs are more complex than SPLDs. PAL (programmable array logic), PLA (programmable logic array), and GAL are the most popular SPLDs (generic array logic).  

What is FPGA?

The customizable logic block (CLB) matrix at the center of field programmable gate arrays (FPGAs), a semiconductor device, is coupled by programmable interconnects. FPGAs can be reprogrammed after production to accommodate certain application or feature requirements. This characteristic sets FPGAs apart from Application Specific Integrated Circuits (ASICs), which are created specifically for certain design requirements. Although one-time programmable (OTP) FPGAs are available, SRAM-based FPGAs, which can be updated as the design changes, are more common. Instead of having a structure resembling that of a PAL or other programmable device, Field Programmable Gate Arrays are structured very much like gate array ASICs. Because of this, FPGAs are excellent for use in ASIC prototyping and other applications where an ASIC will eventually be implemented.  

Video related to CPLD and FPGA

 

The basic structure of CPLD

CPLD Architecture

As a development of PAL, CPLD is made up of several PAL structures called macrocells. Each macrocell in the CPLD package has access to every input pin, whereas each macrocell has a specific output pin. The following graphic shows the block diagram of a CPLD.

Figure 1: CPLDs block diagram We can see from the block diagram that a CPLD is made up of several macrocells or function blocks. A programmable interconnect, also known as GIM, is used to connect the macrocells (global interconnection matrix). Several logic circuits can be built by rearranging the GIM. CPLDs use digital I/Os to communicate with external devices.  

CPLD structure

The structure of CPLD is based on the product term (Product-Term), and the basic structure of CPLD is introduced with Xilinx's XC9500XL series chip as an example. The CPLD can be divided into three parts: Function Block, FastCONNECT Ⅱ SwitchMatrix, and I/O control module. Each function block consists of a programmable array, a product term allocator, and 18 macrocells, and the structure of the function block is shown in the picture. The I/O control module is responsible for controlling the electrical characteristics of the input outputs, such as setting open collector outputs, tri-state outputs, etc. In Figure 2, I/O/GCK, I/O/GSR, and 1/0/GTS are the global clock, global reset, and global output enable signals, which are connected to each function module in the CPLD with a dedicated line.

Figure 2: Internal structure of CPLD based on product term The CPLD's fundamental component, the macro cell, implements the fundamental logic operations. Figure 3 shows the basic structure of a macro cell. The left side of Figure 3 is a product term array, which is actually an array of with or without, and each cross 'point is programmable, and if it is on, it realizes the "with" logic and completes the combination logic together with the product term allocator behind. The right side of Figure 3 is a programmable flip-flop, which can be configured as a D flip-flop or T flip-flop, and its clock and clear inputs can be programmed to use a dedicated global clear and global clock, or use the clock and clear generated by the internal logic (product term array). If the trigger is not needed, this trigger can also be bypassed, and the signal output directly to the interconnect matrix or output to the I/0 pin.

Figure 3: Microcells structure of CPLD  

CPLD logic implementation principle

The following is an example of a simple circuit that specifies how the CPLD implements logic using the above structure, and the circuit is shown in Figure 4.

Figure 4: Simple logic circuit Assuming that the output of combinational logic is f, then f = (A x B) * C * (!D) = A * C *!D + B * C *!D (with !D denoting the "non" of D), the CPLD will implement combinational logic f in the same way as in Figure 5.  

Figure 5: Logic achievement of CPLD   A, B, C, and D are input from the pins of the PLD chip and enter the interconnect matrix, which internally generates 8 outputs A, A, B, B, C, C, D, and D. Each fork in Figure 5 indicates connected (programmable fuse conduction), so we get f = fl + 12 = (A * C *!D) + (B * C *!D) so that the combinational logic is implemented. In Figure 4, the implementation of the D flip-flop is relatively simple and is directly implemented using the programmable D flip-flop in the macro cell. The clock signal CLK is input from the I/O pin into the internal global clock dedicated channel of the chip, which is directly connected to the clock side of the programmable flip-flop. The result is output to the chip pins from the programmable flip-flop's output, which is coupled to the I/O pin. Consequently, the CPLD completes the work of the circuit depicted in Figure 4. All these steps are done automatically by the software and do not require human intervention.   The circuit in Figure 4 is a very simple example that can be done with only one macro cell. However, for a complex circuit, one macro cell is impossible to implement. The output of the macro cell can also be connected to the interconnection matrix, which can then be used as the input of another macro cell. Next, it is necessary to connect several macro cells using parallel extensions and shared extensions. This way the CPLD can implement more complex logic. This kind of CPLD based on the product term is basically manufactured by EEPROM and Flash, and it can work as soon as it is powered on, without the need of other chips to cooperate.  

How does CPLD work?

CPLD develops exceptionally dense, quick, and energy-efficient programmable logic devices using CMOS EPROM, EEPROM, flash memory, and SRAM programming technologies. They fall under the category of large-scale integrated circuits and are relatively vast in scale and complicated in structure. A CPLD is a type of digital integrated circuit that lets users build custom logic circuits to suit their needs. The fundamental method of design is to transfer the code to the target chip via the download cable ("in-system" programming), realize the designed digital system, and then generate the corresponding target file using the integrated development software platform and hardware description language.  

The basic structure of FPGA

FPGA Architecture

The basic FPGA architecture uses modules of three different types. These include I/O blocks or pads (CLB), switch matrices, connector lines, and programmable logic blocks (CLB). The basic FPGA architecture is made up of two-dimensional arrays of logic blocks, which the user can link in any order. The functions of an FPGA architectural module are covered in this article. A CLB (Configurable Logic Block) contains digital inputs, outputs, and logic. It executes user logic. The logic blocks are given guidance by the interconnects so they can carry out the user logic. Logic-based switching between interconnects is provided by the switch matrix. Many applications are connected to the outside world using I/O pads.  

FPGA basics

Several logic blocks make compose a single CLB (Figure 5). The lookup table (LUT) of an FPGA is one of its distinctive features. A LUT stores a predetermined list of logic outputs for any combination of inputs; LUTs with four to six input bits are typical. Flip-flops, complete adders, and multiplexers are a few examples of popular logic operations. The number and configuration of the CLB's components vary depending on the device; the streamlined example in Figure 2 has two three-input LUTs (1), an FA (3), a D-type flip-flop (5), as well as a normal mux (2) and two muxes that are programmed into the FPGA.    

Figure 6: A simplified CLB The condensed CLB can work in one of two ways. The LUT outputs and a carry input from another CLB are sent as inputs to the FA in arithmetic mode. In normal mode, the LUTs are coupled with Mux 2 to produce a four-input LUT. The FA output or the LUT output is chosen by Mux 4. Using the D flip-flop, Mux 6 determines if the operation is asynchronous or synchronized to the FPGA clock. The more sophisticated CLBs present in current-generation FPGAs may conduct many operations with only one block and can be linked to carry out more complex functions like multipliers, registers, counters, and even operations for digital signal processing (DSP).  

How does FPGA work?

Programmable logic, often known as programmable hardware, is a category of devices that includes FPGAs. An FPGA can be configured to be almost any digital circuit you desire, despite the fact that it doesn't actually accomplish anything on its own. The magic in this situation is that nothing actually alters. The FPGA just needs to be loaded with a configuration for it to begin functioning like the desired circuit. No trouble, no jumper wires, and no soldering. Then, an FPGA can be modified to act like yet another circuit, and still another, and yet another. Because the setup is RAM-based, it may essentially be changed as often as needed. Despite the fact that we discuss using FPGAs to build digital circuits, you don't normally construct designs for them by drawing diagrams. Should you really create a schematic, the size and complexity of the circuits that FPGAs may include would become quite difficult? Instead, you can utilize the tools to design a circuit that matches the behavior of the circuit you want by describing the desired behavior.  

CPLD vs. FPGA Applications

CPLD Applications

• Complicated programmable logic devices are perfect for demanding control applications that require great performance.
• Digital designs can use CPLD to carry out bootloader duties.
• Field programmable gate array configuration data are loaded from non-volatile memory using CPLD technology.
• They are typically employed in modest design tasks like address decoding.
• Due to their small size and low power consumption, CPLDs are often employed in a variety of applications, such as in price-sensitive, battery-operated portable devices.

 

FPGA Applications

The wide range of applications that FPGAs are useful for has fueled their meteoric ascent over the past ten years. Applications, where an FPGA is specifically used, include digital signal processing, bioinformatics, device controllers, software-defined radio, random logic, ASIC prototyping, medical imaging, computer hardware emulation, integrating multiple SPLDs, voice recognition, cryptography, filtering, communication encoding, and many more. FPGAs are primarily used in specialized, low-volume vertical applications. The top businesses invest in these low-volume applications' hardware costs per unit. The improved performance dynamics and cost have now increased the number of practical applications.  

FPGA vs. CPLD

 

FPGA	CPLD
FPGA, on the other hand, stands for field programmable gate arrays.	Complex Programmable Logic Devices are known as CPLDs.
RAM serves as the foundation of an FPGA, a digital logic chip.	CPLDs, on the other hand, are EEPROM-based.
CPLD delays are much more predictable than FPGA delays.	Since CPLD has nonvolatile memory, it is protected more than FPGA.
FPGA falls under the fine-grain category.	CPLD, on the other hand, is coarse grain.
FPGA is similar to a Gate array.	However, the CPLD is equivalent to the PAL.
Internal routing has no impact on the performance of FPGA, which is trustworthy.	The performance of CPLD, on the other hand, is inconsistent and dependent on routing.
FPGA has more extensive power usage.	The power consumption of CPLD is lower in contrast.
Complex apps are a good fit for FPGA.	Contrarily, the CPLD performs better with simpler applications.
FPGAs can contain up to 100,000 small logic blocks.	Comparatively, CPLDs can only store a few thousand logic blocks.
Contrarily, an FPGA is an integrated circuit that is primarily designed to be modified by a client or a developer following production.	The operation of digital systems is aided by an integrated circuit known as a CPLD.

 

The conclusion between CPLD and FPGA

Simple programmable logic devices (SPLDs) and complex programmable logic devices (CPLDs), which are less sophisticated components, enable the migration from discrete logic devices to entry-level FPGAs. The key characteristics of entry-level FPGAs are low power consumption, low logic density, and minimal complexity per chip. Devices with enhanced functionality add functional blocks with particular functions: A few examples include high-speed transceivers, Ethernet MACs, PCI express controllers, phase-locked loops (PLLs), high-speed serializers, and deserializes. These building elements can either be developed as standalone circuits (hard IP) or implemented using CLBs (soft IP). Hard IP blocks boost performance at the expense of reconfigurability. The FPGA product family's most advanced system-on-chip (SoC) components integrate the FPGA architecture, hard IP, and a microprocessor CPU core into a single unit. A SoC FPGA provides more integration, reduced power consumption, a smaller board footprint, and higher-bandwidth communication between the core and additional blocks when compared to standalone devices.