Linear Technology
LTC6403IUD-1#PBF
FPGAs (Field Programmable Gate Array)
LTC6403IUD-1#PBF
2-LTC6403IUD-1#PBF
0.5mm 16 Amplifier LTC6403 3V 16-WFQFN Exposed Pad
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LTC6403IUD-1#PBF Description
Tech Specifications
Low-Bias
NO
Unity Gain BW-Nom
200000 kHz
Input Offset Voltage-Max
2000μV
Average Bias Current-Max (IIB)
25μA
Surface Mount
YES
Height Seated (Max)
0.8mm
Number of Functions
1
Common-mode Reject Ratio-Min
55 dB
Package / Case
16-WFQFN Exposed Pad
Terminal Form
NO LEAD
Operating Temperature (Max)
85°C
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Supply Current-Max
12.1mA
Neg Supply Voltage-Max (Vsup)
-5.5V
HTS Code
8542.33.00.01
Architecture
VOLTAGE-FEEDBACK
Programmable Power
NO
Mounting Type
Surface Mount
Pin Count
16
Input Offset Current-Max (IIO)
5μA
Packaging
Tube
Supply Voltage Limit-Max
5.5V
Terminal Pitch
0.5mm
Operating Temperature (Min)
-40°C
Terminal Finish
Matte Tin (Sn)
Terminal Position
QUAD
Low-Offset
YES
JESD-30 Code
S-PQCC-N16
Number of Terminations
16
Supply Voltage
3V
ECCN Code
EAR99
Width
3mm
Qualification Status
Not Qualified
RoHS Status
ROHS3 Compliant
Common Mode Rejection Ratio
72 dB
Applications
Data Acquisition
-3db Bandwidth
200MHz
Micropower
NO
Slew Rate
200 V/us
JESD-609 Code
e3
Factory Lead Time
8 Weeks
Time@Peak Reflow Temperature-Max (s)
30
Peak Reflow Temperature (Cel)
260
Type
ADC Driver
Length
3mm
Part Status
Active
Published
2009
Power
NO
Wideband
YES
Temperature Grade
INDUSTRIAL
Base Part Number
LTC6403
LTC6403IUD-1#PBF Documents
Download datasheets and manufacturer documentation for LTC6403IUD-1#PBF
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